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    Wafer level & Fan Out Packaging

    Wafer level & Fan Out Packaging

    JCET offers wafer level technologies for the following package options:

    ? eWLB (embedded Wafer Level Ball Grid Array)
    ? eWLCSP (encapsulated Wafer Level Chip Scale Packages)
    ? WLCSP (Wafer Level Chip Scale Packages)
    ? IPD (Integrated Passive Devices)
    ? ECP (Encapsulated Chip Package)
    ? RFID (Radio Frequency Identification)

    Today’s consumers are looking for powerful, multi-functional electronic devices with unprecedented performance and speed, yet small, then and low cost.  This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, then, low cost device.  JCET is an industry leader in providing a comprehensive platform of wafer level technology solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP), Integrated Passive Devices (IPD), Through Silicon Via (TSV), Encapsulated Chip Package (ECP), and Radio Frequency Identification (RFID).

    Breakthrough FlexLineTM Manufacturing Approach

    Our innovative approach to wafer level manufacturing, known as the FlexLineTM method, provides customers freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow.  This FlexLine manufacturing method is a significant paradigm shift from conventional wafer level manufacturing, and delivers an unmatched level of flexibility and cost savings for both Fan-In and Fan-Out wafer level packaging.


    The FlexLine approach provides freedom from wafer diameter constraints while enabling supply chain simplification and significant cost reductions not possible with conventional wafer level manufacturing.

    Versatile Technology Platform for 2.5D and 3D Integration

    The FlexLine approach provides freedom from wafer diameter constraints while enabling supply chain simplification and significant cost reductions not possible with conventional wafer level manufacturing.

    ? Higher performance
    ? Higher bandwidth
    ? Higher frequencies
    ? Thinner package profiles


    Contact Us |  Customer |  Legal
    Copyright @ JCET? Group? Co., Ltd.
    苏ICP备05082751号-1 32028102000607
    千亿体育|官方网
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